booth multiplier error in verilog -

i have written

module booth(num1,num2,prod);   input [22:0] num1,num2; output [45:0] prod; reg[22:0]num1_bar; reg[46:0]sub_1; reg [22:0]temp; reg [2:0]sel; reg [22:0]add; reg [22:0]result; reg [22:0]temp2;   @* begin  temp = ~ num1;  num1_bar = temp + 'b00000000000000000000001;  sub_1 = {'b00000000000000000000000, num2, 1'b0};  end  integer i; @* begin     for( = 0; < 22; = i+1) begin          sel = sub_1[2:0];          if(sel == 2'b10) begin              add = sub_1[46:24] + num1_bar;              sub_1 ={add[22],add,sub_1[23:1]};         end          else if(sel == 2'b01) begin              add = sub_1[46:24] + num1 ;              sub_1 ={add[22],add,sub_1[23:1]};         end         else begin              sub_1= {sub_1[46] ,sub_1[46:1]};         end     end      temp2 = ~ sub_1[24:1];      result = 23'b00000000000000000000001 + temp2;      prod <= result; end endmodule 

i have written above code 23*23 booth multiplier, have got errors in code. please me out. have mentioned errors below:

program summary new
xst error hdlcompilers:247 - "booth.v" line 59 reference vector wire 'prod' not legal reg or variable lvalue new
xst error hdlcompilers:44 - "booth.v" line 59 illegal left hand side of blocking assignment new