Can I pass a clock signal as an input argument in a Verilog task? -

i writing testbench in vcs(g-2012.09) verify spi module.

here task byte spi master:

task get_byte; begin     repeat(8) @(posedge spck)     begin         if (spss == 1'b0)             tmp = {tmp[6:0], mosi};     end     $display ("[time:%dns]---->get byte: 0x%h", $stime, tmp); end endtask 

it works. want parameterize task , replace code with:

task get_byte;     input clk, oen, din;     output [7:0] byte; begin     byte = 8'd0;     repeat(8) @(posedge clk)     begin         if (oen == 1'b0)             byte = {byte[6:0], din};     end     $display ("[time:%dns]---->get byte: 0x%h", $stime, byte); end endtask 

but when called task get_byte(spck, spss, mosi, tmp) , run testbench in vcs, stucked. seemed spck did not pass work clk inside task.

so there rule clock signal can not used input argument within task or did make wrong?

in 1 of old stackoverflow questions can find following answer:

in verilog arguments passed tasks value. means value of clock fixed lifetime of call task. task never find posedge of clock, , wait forever.

so answer is: can use clk input argument task, won't work "standard" clock.